The present disclosure relates to an arbitration circuit and, more particularly, to an arbitration circuit configured to optimize bus control between master and slave and to a method of controlling the arbitration circuit.
With complicated and large scale semiconductor integrated circuits based on design techniques such as SoC (System on a Chip) for integrating various types of semiconductor chips into one, two or more devices may be connected to one device via a bus, these two or more devices are configured to control the connected device. In what follows, the devices to be controlled are referred to slaves and the devices that control others are referred to as masters. The masters may include a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), a GPU (Graphics Processing Unit), and so on. The slaves may include a memory controller, an interface port, a video memory, and so on.
In the case where there are two or more masters for a slave, an arbitration circuit is arranged, in which each master transmits a request signal to the arbitration circuit for requesting the use of a bus over which data is transmitted. In order to prevent bus contention caused by the masters and optimize bus control, the arbitration circuit arbitrates the requests from the masters. Next, the arbitration circuit transmits a grant signal to a master selected by the bus arbitration, thereby granting the request for the bus.
The arbitration circuit executes bus arbitration in various ways. For example, there are fixed priority method in which the priority levels between masters in the use of bus are determined in advance and a round-robin method in which the masters are equally handled to grant requests sequentially.
In addition, there are a method obtained by combining the fixed priority level and the round-robin method and a method in which the bus occupancy of each master is determined in advance. The bus occupancy herein denotes a bus occupancy time and the number of transfer words that are necessary for one data processing operation.
The employment of the methods mentioned above for example depends on application programs for use in the control of slaves by a master. However, in the development stage of hardware, no specific use cases are established, so that it is often unclear what kinds of application programs will be executed. This makes it difficult to optimize the operations of the arbitration circuit for executing bus control operations in the initial stage of development. Besides, optimum bus control may differ from one use case to another, thereby present problems that bus control is found to have not been optimized and contention is caused between bus uses after the completion of the hardware design of the arbitration circuit. If any of these problems emerges on any of actual bus arbitration circuits, hardware redo must be done to increase the cost.
In order to circumvent above-mentioned problems, a circuit was proposed in which a priority register to which the priority of each master is set is arranged to change the priorities of the masters by rewriting the preset priority levels without doing hardware redesign (refer to Japanese Patent Laid-open No. Hei 8-123634 for example). According to this proposed technology, bus control can be optimized without redesigning the hardware if the priority levels of masters have been changed owning to the changes of application specifications for example.
In the case where the bus occupancy of each master is determined in advance, an apparatus was proposed in which the bus occupancy of each data processing operation is stored, in storage means, for each master to change the bus occupancies by rewriting this storage means (refer to Japanese Patent Laid-open No. 2000-132505 for example). With such an apparatus, a fixed priority level is preset for each master. If, while a master having a lower priority level is occupying the bus, a master having a higher priority level than that of the bus occupying master requests data transfer, the proposed apparatus can grant bus control to the master having the higher priority level. According to this proposed technology, bus control can be optimized without redesigning the hardware if the priority levels of masters have been changed owning to the changes of application specifications for example.